Statistical estimator for simultaneous noise and mismatch suppression in SAR ADC

I. Banerjee, A. Sanyal

Research output: Contribution to journalArticlepeer-review


A statistical estimator based on maximum-likelihood estimation theory is developed to simultaneously reduce capacitor mismatch and noise in a successive approximation register analogue-to-digital converter (SAR ADC). After the SAR ADC has finished quantisation, the residue voltage is available at the comparator input and is estimated accurately by using the statistical estimator. The ADC resolution is improved by subtracting the estimated residue from the digital output. The same technique of residue extraction is used to estimate mismatches in the capacitive digital-to-analogue converter. A 7 dB improvement is shown in signal-to-noise-plus-distortion ratio by using the statistical estimator for an 11-bit SAR over a wide range of capacitance mismatch and ADC noise.

Original languageEnglish (US)
Pages (from-to)773-775
Number of pages3
JournalElectronics Letters
Issue number12
StatePublished - Jun 8 2017

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


Dive into the research topics of 'Statistical estimator for simultaneous noise and mismatch suppression in SAR ADC'. Together they form a unique fingerprint.

Cite this