TY - GEN
T1 - Practical limitations of state-of-the-art passive printed circuit board power delivery networks for high performance compute systems
AU - Smutzer, Chad M.
AU - Gilbert, Barry K.
AU - Daniel, Erik S.
PY - 2013
Y1 - 2013
N2 - Trends in high performance computing (HPC) systems point to ever-decreasing power delivery network (PDN) impedances. While there is no particular theoretical minimum impedance, practical limitations present boundaries which will be difficult to exceed. In this paper, we explore specifically the practical limitations of the printed circuit board (PCB) portion of the PDN, concluding that useful implementations will be limited to on the order of 0.2 mOhms below 1 MHz, rising to roughly 0.4 mOhms at 10 MHz, and increasing with frequency thereafter.
AB - Trends in high performance computing (HPC) systems point to ever-decreasing power delivery network (PDN) impedances. While there is no particular theoretical minimum impedance, practical limitations present boundaries which will be difficult to exceed. In this paper, we explore specifically the practical limitations of the printed circuit board (PCB) portion of the PDN, concluding that useful implementations will be limited to on the order of 0.2 mOhms below 1 MHz, rising to roughly 0.4 mOhms at 10 MHz, and increasing with frequency thereafter.
UR - http://www.scopus.com/inward/record.url?scp=84881512581&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84881512581&partnerID=8YFLogxK
U2 - 10.1109/SaPIW.2013.6558326
DO - 10.1109/SaPIW.2013.6558326
M3 - Conference contribution
AN - SCOPUS:84881512581
SN - 9781467356787
T3 - 2013 17th IEEE Workshop on Signal and Power Integrity, SPI 2013
BT - 2013 17th IEEE Workshop on Signal and Power Integrity, SPI 2013
T2 - 2013 17th IEEE Workshop on Signal and Power Integrity, SPI 2013
Y2 - 12 May 2013 through 15 May 2013
ER -