TY - JOUR
T1 - Fully Integrated Analog Machine Learning Classifier Using Custom Activation Function for Low Resolution Image Classification
AU - Tannirkulam Chandrasekaran, Sanjeev
AU - Jayaraj, Akshay
AU - Elkoori Ghantala Karnam, Vinay
AU - Banerjee, Imon
AU - Sanyal, Arindam
N1 - Funding Information:
Manuscript received August 28, 2020; revised November 25, 2020; accepted December 21, 2020. Date of publication January 28, 2021; date of current version February 23, 2021. This work was supported in part by the National Science Foundation under Grant CCF-1948331. This article was recommended by Associate Editor R. Rieger. (Corresponding author: Sanjeev Tannirkulam Chandrasekaran.) Sanjeev Tannirkulam Chandrasekaran, Vinay Elkoori Ghantala Karnam, and Arindam Sanyal are with the Department of Electrical Engineering, University at Buffalo, Buffalo, NY 14260 USA (e-mail: stannirk@buffalo.edu). Akshay Jayaraj is with Intel Corporation, Folsom, CA 95630 USA.
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2021/3
Y1 - 2021/3
N2 - This paper presents fully-integrated analog neural network classifier architecture for low resolution image classification that eliminates memory access. We design custom activation functions using single-stage common-source amplifiers, and apply a hardware-software co-design methodology to incorporate knowledge of the custom activation functions into the training phase to achieve high accuracy. Performing all computations entirely in the analog domain eliminates energy cost associated with memory access and data movement. We demonstrate our classifier on multinomial classification task of recognizing down-sampled handwritten digits from MNIST dataset. Fabricated in 65nm CMOS process, the measured energy consumption for down-sampled MNIST dataset is 173pJ/classification, which is 3\times better than state-of-the-art. The prototype IC achieves mean classification accuracy of 81.3% even after down-sampling the original MNIST images by 96% from 28\times 28 pixels to 5\times 5 pixels.
AB - This paper presents fully-integrated analog neural network classifier architecture for low resolution image classification that eliminates memory access. We design custom activation functions using single-stage common-source amplifiers, and apply a hardware-software co-design methodology to incorporate knowledge of the custom activation functions into the training phase to achieve high accuracy. Performing all computations entirely in the analog domain eliminates energy cost associated with memory access and data movement. We demonstrate our classifier on multinomial classification task of recognizing down-sampled handwritten digits from MNIST dataset. Fabricated in 65nm CMOS process, the measured energy consumption for down-sampled MNIST dataset is 173pJ/classification, which is 3\times better than state-of-the-art. The prototype IC achieves mean classification accuracy of 81.3% even after down-sampling the original MNIST images by 96% from 28\times 28 pixels to 5\times 5 pixels.
KW - Machine learning
KW - analog neural network
KW - custom activation function
KW - low resolution image classification
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U2 - 10.1109/TCSI.2020.3047331
DO - 10.1109/TCSI.2020.3047331
M3 - Article
AN - SCOPUS:85100479472
SN - 1549-8328
VL - 68
SP - 1023
EP - 1033
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 3
M1 - 9337886
ER -