Efficient circuit-level implementation of knuth-based balanced and nearly-balanced codes

Coding schemes are often used in high-speed processor-processor or processor-memory busses in digital systems. In particular, we have introduced (in a 2012 DesignCon paper) a zero sum (ZS) signaling method which uses balanced or nearly-balanced coding to reduce simultaneous switching noise (SSN) in a single-ended bus to a level comparable to that of differential signaling. While several balanced coding schemes are known, few papers exist that describe the necessary digital hardware implementations of (known) balanced coding schemes, and no algorithms had previously been developed for nearly-balanced coding. In this work, we extend a known balanced coding scheme to accommodate nearly-balanced coding and demonstrate a range of coding and decoding circuits through synthesis in 65 nm CMOS. These hardware implementations have minimal impact on the energy efficiency and area when compared to current serializer/deserializers (SerDes) at clock rates which would support SerDes integration.