Digital System Design in the Presence of Single Event Upsets

We consider the effects of single event upsets (SEU) on digital systems, and show techniques for designing reliable systems with current levels of SEU protection. We consider three main systems: main memory, logic, and cache memory. We also describe a design of main and cache memory subsystems which are SEU protected. We consider three main subsystems: main memory, logic, and cache memory. With SEU defined in bit days p, and using single error correction we show that for all subsystems considered we can obtain an effective upset rate which is proportional to the product of p²and the time between corrections, or scrub time. In particular, we have used data for memory chip size and performance derived from the Gallium Arsenide (GaAs) pilot lines funded by the Defense Advanced Research Projects Agency (DARPA) throughout the 1980s.