A highly parallel AES-GCM core for authenticated encryption of 400 Gb/s network protocols

Benjamin Buhrow; Karl Fritz; Barry Kent Gilbert; Erik Daniel

doi:10.1109/ReConFig.2015.7393321

A highly parallel AES-GCM core for authenticated encryption of 400 Gb/s network protocols

Benjamin Buhrow, Karl Fritz, Barry Kent Gilbert, Erik Daniel

Physiology & Biomedical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

11 Scopus citations

Abstract

The Advanced Encryption Standard (AES) together with the Galois Counter Mode (GCM) of operation has been approved for use in several high throughput network protocols to provide authenticated encryption. However, the demand for continued increase in network bandwidth has not abated and we anticipate the need for continual performance improvement of AES-GCM in hardware. Additionally, as data interfaces become wider and segmented, existing methods of GCM parallelization become inefficient. This paper presents a novel scalable architecture for highly parallel implementations of AES-GCM that can process multiple separately-keyed packets simultaneously every clock cycle. We demonstrate throughputs of 482 Gb/s in a single Xilinx Virtex Ultrascale FPGA and describe how the architecture can be used to achieve over 800 Gb/s in a system comprising multiple FPGAs.

Original language	English (US)
Title of host publication	2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	9781467394062
DOIs	https://doi.org/10.1109/ReConFig.2015.7393321
State	Published - Jan 25 2016
Event	International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015 - Riviera Maya, Mexico Duration: Dec 7 2015 → Dec 9 2015

Other

Other	International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015
Country/Territory	Mexico
City	Riviera Maya
Period	12/7/15 → 12/9/15

Keywords

FPGA
Galois Counter Mode
high throughput
multiple packets per clock cycle
scalable
segmented bus

ASJC Scopus subject areas

Hardware and Architecture
Software

Access to Document

10.1109/ReConFig.2015.7393321

Cite this

A highly parallel AES-GCM core for authenticated encryption of 400 Gb/s network protocols. / Buhrow, Benjamin; Fritz, Karl; Gilbert, Barry Kent et al.
2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015. Institute of Electrical and Electronics Engineers Inc., 2016. 7393321.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Buhrow, B, Fritz, K, Gilbert, BK & Daniel, E 2016, A highly parallel AES-GCM core for authenticated encryption of 400 Gb/s network protocols. in 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015., 7393321, Institute of Electrical and Electronics Engineers Inc., International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015, Riviera Maya, Mexico, 12/7/15. https://doi.org/10.1109/ReConFig.2015.7393321

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AB - The Advanced Encryption Standard (AES) together with the Galois Counter Mode (GCM) of operation has been approved for use in several high throughput network protocols to provide authenticated encryption. However, the demand for continued increase in network bandwidth has not abated and we anticipate the need for continual performance improvement of AES-GCM in hardware. Additionally, as data interfaces become wider and segmented, existing methods of GCM parallelization become inefficient. This paper presents a novel scalable architecture for highly parallel implementations of AES-GCM that can process multiple separately-keyed packets simultaneously every clock cycle. We demonstrate throughputs of 482 Gb/s in a single Xilinx Virtex Ultrascale FPGA and describe how the architecture can be used to achieve over 800 Gb/s in a system comprising multiple FPGAs.

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A highly parallel AES-GCM core for authenticated encryption of 400 Gb/s network protocols

Abstract

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Keywords

ASJC Scopus subject areas

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