AN efficient architecture for hardware implementations of image processing algorithms

Farzad Khalvati; Hamid R. Tizhoosh

doi:10.1109/CIIP.2009.4937875

AN efficient architecture for hardware implementations of image processing algorithms

Farzad Khalvati, Hamid R. Tizhoosh

Artificial Intelligence and Informatics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This work presents a new performance improvement technique for hardware implementations of non-recursive convolution based image processing algorithms. It combines an advanced data flow technique (instruction reuse) proposed in modern microprocessor design with the value locality of image data to develop a method, window memoization, that increases the throughput with minimal cost in area and accuracy. We implement window memoization as a 2-wide superscalar pipeline such that it consumes significantly less area than conventional 2-wide superscalar pipelines. As a case study, we have applied window memoization to Kirsch edge detector. The average speedup factor was 1.76 with only 25% extra hardware.

Original language	English (US)
Title of host publication	2009 IEEE Symposium on Computational Intelligence in Image Processing, CIIP 2009 - Processing
Pages	20-26
Number of pages	7
DOIs	https://doi.org/10.1109/CIIP.2009.4937875
State	Published - 2009
Event	2009 IEEE Symposium on Computational Intelligence in Image Processing, CIIP 2009 - Nashville, TN, United States Duration: Mar 30 2009 → Apr 2 2009

Publication series

Name	2009 IEEE Symposium on Computational Intelligence in Image Processing, CIIP 2009 - Proceedings

Conference

Conference	2009 IEEE Symposium on Computational Intelligence in Image Processing, CIIP 2009
Country/Territory	United States
City	Nashville, TN
Period	3/30/09 → 4/2/09

ASJC Scopus subject areas

Artificial Intelligence
Computational Theory and Mathematics
Computer Vision and Pattern Recognition

Access to Document

10.1109/CIIP.2009.4937875

Cite this

Khalvati, F., & Tizhoosh, H. R. (2009). AN efficient architecture for hardware implementations of image processing algorithms. In 2009 IEEE Symposium on Computational Intelligence in Image Processing, CIIP 2009 - Processing (pp. 20-26). Article 4937875 (2009 IEEE Symposium on Computational Intelligence in Image Processing, CIIP 2009 - Proceedings). https://doi.org/10.1109/CIIP.2009.4937875

AN efficient architecture for hardware implementations of image processing algorithms. / Khalvati, Farzad; Tizhoosh, Hamid R.
2009 IEEE Symposium on Computational Intelligence in Image Processing, CIIP 2009 - Processing. 2009. p. 20-26 4937875 (2009 IEEE Symposium on Computational Intelligence in Image Processing, CIIP 2009 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Khalvati, F & Tizhoosh, HR 2009, AN efficient architecture for hardware implementations of image processing algorithms. in 2009 IEEE Symposium on Computational Intelligence in Image Processing, CIIP 2009 - Processing., 4937875, 2009 IEEE Symposium on Computational Intelligence in Image Processing, CIIP 2009 - Proceedings, pp. 20-26, 2009 IEEE Symposium on Computational Intelligence in Image Processing, CIIP 2009, Nashville, TN, United States, 3/30/09. https://doi.org/10.1109/CIIP.2009.4937875

@inproceedings{2d9cc7a8042744b18dbbe1ba8bff6cbe,

title = "AN efficient architecture for hardware implementations of image processing algorithms",

abstract = "This work presents a new performance improvement technique for hardware implementations of non-recursive convolution based image processing algorithms. It combines an advanced data flow technique (instruction reuse) proposed in modern microprocessor design with the value locality of image data to develop a method, window memoization, that increases the throughput with minimal cost in area and accuracy. We implement window memoization as a 2-wide superscalar pipeline such that it consumes significantly less area than conventional 2-wide superscalar pipelines. As a case study, we have applied window memoization to Kirsch edge detector. The average speedup factor was 1.76 with only 25% extra hardware.",

author = "Farzad Khalvati and Tizhoosh, {Hamid R.}",

year = "2009",

doi = "10.1109/CIIP.2009.4937875",

language = "English (US)",

isbn = "9781424427604",

series = "2009 IEEE Symposium on Computational Intelligence in Image Processing, CIIP 2009 - Proceedings",

pages = "20--26",

booktitle = "2009 IEEE Symposium on Computational Intelligence in Image Processing, CIIP 2009 - Processing",

note = "2009 IEEE Symposium on Computational Intelligence in Image Processing, CIIP 2009 ; Conference date: 30-03-2009 Through 02-04-2009",

}

TY - GEN

T1 - AN efficient architecture for hardware implementations of image processing algorithms

AU - Khalvati, Farzad

AU - Tizhoosh, Hamid R.

PY - 2009

Y1 - 2009

N2 - This work presents a new performance improvement technique for hardware implementations of non-recursive convolution based image processing algorithms. It combines an advanced data flow technique (instruction reuse) proposed in modern microprocessor design with the value locality of image data to develop a method, window memoization, that increases the throughput with minimal cost in area and accuracy. We implement window memoization as a 2-wide superscalar pipeline such that it consumes significantly less area than conventional 2-wide superscalar pipelines. As a case study, we have applied window memoization to Kirsch edge detector. The average speedup factor was 1.76 with only 25% extra hardware.

AB - This work presents a new performance improvement technique for hardware implementations of non-recursive convolution based image processing algorithms. It combines an advanced data flow technique (instruction reuse) proposed in modern microprocessor design with the value locality of image data to develop a method, window memoization, that increases the throughput with minimal cost in area and accuracy. We implement window memoization as a 2-wide superscalar pipeline such that it consumes significantly less area than conventional 2-wide superscalar pipelines. As a case study, we have applied window memoization to Kirsch edge detector. The average speedup factor was 1.76 with only 25% extra hardware.

UR - http://www.scopus.com/inward/record.url?scp=67650491196&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=67650491196&partnerID=8YFLogxK

U2 - 10.1109/CIIP.2009.4937875

DO - 10.1109/CIIP.2009.4937875

M3 - Conference contribution

AN - SCOPUS:67650491196

SN - 9781424427604

T3 - 2009 IEEE Symposium on Computational Intelligence in Image Processing, CIIP 2009 - Proceedings

SP - 20

EP - 26

BT - 2009 IEEE Symposium on Computational Intelligence in Image Processing, CIIP 2009 - Processing

T2 - 2009 IEEE Symposium on Computational Intelligence in Image Processing, CIIP 2009

Y2 - 30 March 2009 through 2 April 2009

ER -

AN efficient architecture for hardware implementations of image processing algorithms

Abstract

Publication series

Conference

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this