@inproceedings{13baf820578547918531b6490990961d,
title = "A Parameterized and Minimal Resource Soft Processor for Programmable Logic",
abstract = "Incorporating a soft processor in a programmable logic system, e.g. a field programmable gate array (FPGA), often requires using a substantial percentage of the logic cells (LC), notably on low-power devices. In this work we present a 32-bit RISC-V soft processor design that uses a serial arithmetic logic unit (ALU). The design can be configured to use less than 5% of the LC resources in a 5K LC low-power FPGA device. Small occupancy soft processors enable complex control and ancillary support to the principal processing and transport paths.",
keywords = "FPGA, Low power, Programmable logic, RISC-V, Sensor-hub, Serial ALU, Soft processor",
author = "Felton, {Christopher L.} and Gilbert, {Barry K.} and Haider, {Clifton R.}",
note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 53rd Asilomar Conference on Circuits, Systems and Computers, ACSSC 2019 ; Conference date: 03-11-2019 Through 06-11-2019",
year = "2019",
month = nov,
doi = "10.1109/IEEECONF44664.2019.9048878",
language = "English (US)",
series = "Conference Record - Asilomar Conference on Signals, Systems and Computers",
publisher = "IEEE Computer Society",
pages = "1601--1605",
editor = "Matthews, {Michael B.}",
booktitle = "Conference Record - 53rd Asilomar Conference on Circuits, Systems and Computers, ACSSC 2019",
}